The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding\nhigh-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a\nsignificant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and\nthus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient\ninterpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm\nbased on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average\nwith acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter\nVLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a\nreconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve\nhigh throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an\noperating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or\nquarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our\nproposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 Ã?â?? 4320@78fps video sequences.
Loading....